TA的首页The Final Test
The Final TestEdmond L. Kyser, Ph.D.Cisco Systems
版权属于作者
Abstract
Manufacturers of complex electronic equipment invariably have a 'Final Test' - a test where product that passes is shipped to the customer, and product that fails is sent to rework for repair. Traditionally, these Final Tests fall into three categories: Burn-In (power on and functional at room temperature for an extended period of time), Conformance (power on and functional at design limit of temperature and possibly other stresses), and Overstress (power on and functional at stresses beyond design limits). The decision of which Final Test to employ is analyzed in this paper in terms of Type I and Type II errors (false failures and false passes), and the conceptual biases commonly found in this decision process.Introduction
In the manufacturing process for complex electronic products, there are many test operations, each of which can be considered a 'confirmation' of the immediately preceding assembly operation. At the conclusion of each test, there are two possible outcomes - the product is either 'shipped' to the next assembly operation or is returned for rework. The 'good' or 'normal' outcome is that the board passes.
In statistical terms [1], we call the good outcome the Null Hypothesis. The Test is designed to confirm the Null Hypothesis. Here we will be concerned with the design of the Test - specifically, what is the criteria for the board to be judged 'good', and how accurate is the Test in confirming this 'goodness'?. Setting aside for the moment the definition of 'good', the situation is as shown in Table 1.
Test: Positive
Test: Negative
Good board
Correct result
Type I error
Bad board
Type II error
Correct result
Table 1Type I and Type II errors
A Type I error - designating a good board as bad - is called the producer's risk, or a false fail. A Type II error - designating a bad board good - is called the consumer's risk, or a false pass. In this case, these are the only types of error possible. A good test will minimize these errors. Burn-in, Conformance and Overstress
It is common for complex electronic products to exhibit the reliability characteristic shown in Figure 1. A high initial failure rate (or parts return rate) is followed by a more-or-less asymptotic decline over a period of time to a steady failure rate, sometimes called the 'mature' failure rate. This is the same characteristic as the front end of the infamous 'bathtub curve'. However, the data in Figure 1 do not show an increasing failure rate as time passes, indicating that there is no evidence of 'end-of-life, or wearout. In what follows, we will use the generic characteristic of Figure 2 for the products being analyzed.
Figure 1Part Replacement rate vs. Time for 5 computer products
Figure 2Generic Field Failure Characteristic
Figure 2 is the metric of success for the benefits of the final Test. We expect product that passes the final test to perform better in the field - that is, to have fewer early life failures, and a larger MTTF.
Consider now three candidates for Final Test - Burn-in, Compliance, and Overstress.
Final Test
Characteristic
Burn-in
Functional test at ambient or elevated temp for extended time
Compliance
Functional test at design limits
Overstress
Functional test beyond design limits
Each of these candidates for Final Test has its champions, its history, its advantages and drawbacks [2,3,4]. The task before the manufacturing test engineer is which to recommend for a specific product, and the task set here in this paper is to systematize the decision.
At this point we have introduced two measures of 'badness' - Type I and Type II errors - and one measure of 'goodness' - MTBF improvement, or early life failure reduction. The three Final Test proposals differ primarily in the level of stress applied. In addition, the error rates at final Test will be Stress level dependent - assuming that the stresses selected are relevant (more on this later). This is illustrated in Figure 3.
Figure 3Type I and Type II errors vs. Stress Level
Several comments are in order relating to Figure 3. Most importantly, it is a metaphor - a model of reality. As the advertisements say, your results may vary. However, the general characteristics of figure 3 are representative of the products that the author has experience with. If Burn-in is performed at ambient conditions with stresses that are close to end user reality, then the Type I error rate (false fails) should be essentially zero. However, Type II errors (false passes) will be relatively high (remember that ALL field failures are by definition Type II errors). The appeal of Burn-in is that it is a low cost, low engineering content, low risk test - and the cost of test escapes is deferred until failed product is returned. It does not typically assure (or test for) product functionality over the entire design stress range. The producing company has promised performance it has decided not to confirm in a Final Test.
A Conformance Test is designed to alleviate the deficiencies of Burn-in, possibly at the cost of increasing Type II errors. For example, a product specified to operate from 0 to 50C, 15% to 85% humidity, +-5% supply voltage, and some maximum load in terms of users or traffic, should be tested at all combinations of these extreme values for a comprehensive Conformation test. In practice, this is seldom done. One alternative is to test at two corners of the conformance space - the 'fast' corner of high temperature and low voltage, and the 'slow' corner of low temperature and high voltage. The expectation for a conformance test is that Type II errors will be reduced and Type I errors will increase, as compared to Burn-in. The appeal of conformance testing is that the stresses are identical with the design criteria, and that it should produce a more robust product that Burn-in.
If only Burn-in and Conformance were represented in Figure 3, the curious engineer would likely ask the following questions: where is the optimum stress level - and could it possibly lie beyond the design/conformance level? After all, the curves for Type I and II errors are continuous through the design limit stress level - the best stress level could very likely be beyond the design limit. The real answers will require an assignment of relative importance to Type I and Type II errors. The use of stresses beyond design limits - overstress testing - was begun in the early 1980's, notably by the US Armed Forces, in an attempt to improve system reliability [5].
COSTS AND BENEFITS
The following cost-benefit analysis was developed in [4] as a method of 'netting out' all the positives and negatives relating to Environmental Stress Screening. The model allows for variables with unknown values to be estimated in terms of probability distributions, and the outcome calculated by Monte Carlo techniques. The output is a probability distribution of Net Present Savings per board tested. The software used was ‘Analytica”, published by Lumina Decision systems [6].
Figure 4 shows the relationships between the variables in the model. The costs of Type I errors are calculated in the node labeled ‘Cost of Test Failures’. The costs of Type II errors are calculated in the node labeled ‘total field Failure cost’. Since field failures occur, on average, at the MTTF, these must be discounted by the Cost of Capital to yield ‘Present Value of FF’, which can then be compared directly to ‘Cost of Test Failures’. The ‘NPS Importance’ node gives the relative importance of the variables in calculating Net Present Value. This will be discussed in a following section.
Figure 4Cost Model Variables and Relationships
It should be clear that cost considerations are not included in the definitions of Type I and Type II errors. The addition of cost in the model above allows us to evaluate the Net Present Savings per board generated by Final Test. The details of this model and the definitions of the mathematical relationships are given in [4]. Here we want to apply the model to 3 very different product scenarios in order to evaluate proposals to strengthen final Test and to reduce Type II errors.Table 4 shows the parameters for 3 products. Case 1 is for a fault-tolerant high-end Server, Case 2 is a Controller with a small imbedded processor, and case 3 is a telecommunications Router. The question in each case is should the Final Test be strengthened to Overstress status.
Variable Name
Units
Comments
Case 1: Server
Case 2: Controller
Case 3: Router
Cost of Inventory
%/week
Includes Depreciation and liquidity effects
Lognormal (0.5, 1.5)
Lognormal (0.5, 1.5)
Lognormal (0.5,1.5)
Test Failure Repair Cost
NP$
Material and Labor costs for debug and repair
Lognormal (1500, 1.5)
Lognormal (8,2)
Lognormal(1000,2)
Time to Repair Test Failure
Weeks
WIP time
Lognormal (6, 1.5)
Lognormal (.5,2)
Lognormal (1, .5)
Replacement Cost of Field Failure
Future$
Material and Labor (warranty costs)
Lognormal (2500, 1.25)
Linear (5,10)
Lognormal(190+0.52H, 1.5)
MTTF of Unscreened Unit
Years
Mean Time To Failure
Lognormal(5, 1.5)
8
Normal(20,2)
Impact of ESS on MTTF
%
Factor by which ESS improves unit MTTF
Normal (25%, 15%)
Normal (20%,15%)
Normal(20%, 15%)
Operational Costs
NP$
Variable cost only (no fixed costs)
Lognormal (50, 1.5)
5
Lognormal(20,2)
Whole Product Cost
NP$
Used to calculate inventory, depreciation, and replacement costs
5000
100
8000
ESS Yield
-
Probability of passing ESS screen
90%
90%
90%
IBP for Field Failure
Future$
A measure of the intangible costs
2500
Linear (20,40)
H/2
Cost of Capital
%/year
Time vs. money discount rate
15%
15%
15%
Table 4Input Variables for 3 Products
Once these values are input into the model, it calculates the probability of achieving Net Present Savings. For the Server, the results are shown in figure 5. Figure 5NPS for Server
From Figure 5, the cumulative probability of breaking even ($0 NPS) occurs at 0.3, meaning that there is a 30% probability of a negative NPS (costs exceed benefits, and the final Test looses money) and 70% probability of a positive NPS. The Expected Value of NPS, which is defined as 50% cumulative probability, is about $180. We expect this version of Final Test to save us $180 per board tested. Therefore, this program should be implemented.
Typically, a few uncertain inputs are responsible for most of the uncertainty in the final result. I have had opponents of overstress testing argue, for example, that the cost of repairing Type I failures would make the entire test worthless. This type of question is best answered by using Importance analysis – which, in statistical terms, is the absolute rank-order correlation between the sample of output values and the sample for each uncertain input. (See [6]).
Figure 6 shows the Importance analysis for the Server. Here we see that ‘Impact of ESS on MTTF’ is an order of magnitude more important than ‘Test Failure Repair Cost’ – and thus, if the model is to be challenged or improved, one should focus on Impact of ESS.
Figure 6Variable Importance for Server
Looking at Figure 7, NPS for an Embedded controller, the cumulative probability of breaking even ($0 NPS) occurs at 0.9, meaning that there is a 90% probability of a negative NPS (costs exceed benefits, and the final Test looses money) and 10% probability of a positive NPS. The Expected Value of NPS, which is defined as 50% cumulative probability, is about -$3.00. We expect this version of Final Test to loose $3 per board tested. Therefore, this program should not be implemented. Looking at the input values, we suspect that this conclusion is dominated by the high reliability of the unscreened board, and the low cost of a field failure.
Figure 7NPS for Controller
Variable importance for the controller is shown in Figure 8. Note that once again the impact of ESS on MTTF is the leading contributor to uncertainty in the final result of NPS. Also, importance is only calculable for variables, not input constants. Therefore, for example, operational costs which were variable for the server and show up on the ‘importance’ chart, are input as constant for the controller, and do not appear on the importance plot.
Figure 8Variable Importance for Controller
Turning to the case of the Router in figure 9, the probability of breaking even ($0 NPS) occurs at 0.4, meaning that there is a 40% probability of a negative NPS (costs exceed benefits, and the final Test looses money) and 60% probability of a positive NPS. The Expected Value of NPS, which is defined as 50% cumulative probability, is $52. We expect this version of Final Test to save us $52 per board tested. Here the risks are high, and the outcome is uncertain. A good policy would be to go back and re-evaluate the input parameters, or to run a preliminary test in an effort to reduce uncertainty.
Figure 9NPS for Router
Router Variable Importance in Figure 10 shows Impact of ESS again the leading cause of uncertainty, but now Test Failure Repair costs are significant.
Figure 10Variable Importance for Router
Finally, we can extract from the preceding analyses the costs of Type I and Type II errors for each of the 3 cases being examined. These results are shown in Table 5. Note particularly how expensive a Type II error is compared to Type I, and the importance of including the cost of money in discounting Type II errors to current dollars for MTTF years. I believe that information like that given in Table 5 can serve well to overcome the reluctance to consider overstress testing. The bias against overstress is often based on fear of creating additional Type I errors.
Server
Controller
Router
Type I error (cost of test fail)
$201.00
$1.13
$146.00
Type II error (field failure)
$5,063.00
$37.50
$8,566.00
MTTF (years)
5
8
20
Type II error in current $
$2,486.00
$14.62
$501.00
Table 5Cost of Type I and Type II errors
Conclusions
Optimizing the final Test can be done in a systematic manner, using statistically represented variables where the true values are unknown at the time of the analysis. The decision of which 'Final Test’ to employ can be analyzed in terms of Type I and Type II errors (false failures and false passes), and calculation of Net Present Savings per board to be realized by the test.Overstress tests can be more effective than either burn-in or conformance, depending on product parameters such as MTTF and cost of repair. The analysis shows that improving the MTTF of the product is the predominately important variable.Each product must be analyzed. Variations from product to product are key, with variables assuming vastly different importance for different products.Type II failures (field failures) are often an order of magnitude more costly than Type I failures (test failures in-house).
References
版权属于作者
Abstract
Manufacturers of complex electronic equipment invariably have a 'Final Test' - a test where product that passes is shipped to the customer, and product that fails is sent to rework for repair. Traditionally, these Final Tests fall into three categories: Burn-In (power on and functional at room temperature for an extended period of time), Conformance (power on and functional at design limit of temperature and possibly other stresses), and Overstress (power on and functional at stresses beyond design limits). The decision of which Final Test to employ is analyzed in this paper in terms of Type I and Type II errors (false failures and false passes), and the conceptual biases commonly found in this decision process.Introduction
In the manufacturing process for complex electronic products, there are many test operations, each of which can be considered a 'confirmation' of the immediately preceding assembly operation. At the conclusion of each test, there are two possible outcomes - the product is either 'shipped' to the next assembly operation or is returned for rework. The 'good' or 'normal' outcome is that the board passes.
In statistical terms [1], we call the good outcome the Null Hypothesis. The Test is designed to confirm the Null Hypothesis. Here we will be concerned with the design of the Test - specifically, what is the criteria for the board to be judged 'good', and how accurate is the Test in confirming this 'goodness'?. Setting aside for the moment the definition of 'good', the situation is as shown in Table 1.
Test: Positive
Test: Negative
Good board
Correct result
Type I error
Bad board
Type II error
Correct result
Table 1Type I and Type II errors
A Type I error - designating a good board as bad - is called the producer's risk, or a false fail. A Type II error - designating a bad board good - is called the consumer's risk, or a false pass. In this case, these are the only types of error possible. A good test will minimize these errors. Burn-in, Conformance and Overstress
It is common for complex electronic products to exhibit the reliability characteristic shown in Figure 1. A high initial failure rate (or parts return rate) is followed by a more-or-less asymptotic decline over a period of time to a steady failure rate, sometimes called the 'mature' failure rate. This is the same characteristic as the front end of the infamous 'bathtub curve'. However, the data in Figure 1 do not show an increasing failure rate as time passes, indicating that there is no evidence of 'end-of-life, or wearout. In what follows, we will use the generic characteristic of Figure 2 for the products being analyzed.
Figure 1Part Replacement rate vs. Time for 5 computer products
Figure 2Generic Field Failure Characteristic
Figure 2 is the metric of success for the benefits of the final Test. We expect product that passes the final test to perform better in the field - that is, to have fewer early life failures, and a larger MTTF.
Consider now three candidates for Final Test - Burn-in, Compliance, and Overstress.
Final Test
Characteristic
Burn-in
Functional test at ambient or elevated temp for extended time
Compliance
Functional test at design limits
Overstress
Functional test beyond design limits
Each of these candidates for Final Test has its champions, its history, its advantages and drawbacks [2,3,4]. The task before the manufacturing test engineer is which to recommend for a specific product, and the task set here in this paper is to systematize the decision.
At this point we have introduced two measures of 'badness' - Type I and Type II errors - and one measure of 'goodness' - MTBF improvement, or early life failure reduction. The three Final Test proposals differ primarily in the level of stress applied. In addition, the error rates at final Test will be Stress level dependent - assuming that the stresses selected are relevant (more on this later). This is illustrated in Figure 3.
Figure 3Type I and Type II errors vs. Stress Level
Several comments are in order relating to Figure 3. Most importantly, it is a metaphor - a model of reality. As the advertisements say, your results may vary. However, the general characteristics of figure 3 are representative of the products that the author has experience with. If Burn-in is performed at ambient conditions with stresses that are close to end user reality, then the Type I error rate (false fails) should be essentially zero. However, Type II errors (false passes) will be relatively high (remember that ALL field failures are by definition Type II errors). The appeal of Burn-in is that it is a low cost, low engineering content, low risk test - and the cost of test escapes is deferred until failed product is returned. It does not typically assure (or test for) product functionality over the entire design stress range. The producing company has promised performance it has decided not to confirm in a Final Test.
A Conformance Test is designed to alleviate the deficiencies of Burn-in, possibly at the cost of increasing Type II errors. For example, a product specified to operate from 0 to 50C, 15% to 85% humidity, +-5% supply voltage, and some maximum load in terms of users or traffic, should be tested at all combinations of these extreme values for a comprehensive Conformation test. In practice, this is seldom done. One alternative is to test at two corners of the conformance space - the 'fast' corner of high temperature and low voltage, and the 'slow' corner of low temperature and high voltage. The expectation for a conformance test is that Type II errors will be reduced and Type I errors will increase, as compared to Burn-in. The appeal of conformance testing is that the stresses are identical with the design criteria, and that it should produce a more robust product that Burn-in.
If only Burn-in and Conformance were represented in Figure 3, the curious engineer would likely ask the following questions: where is the optimum stress level - and could it possibly lie beyond the design/conformance level? After all, the curves for Type I and II errors are continuous through the design limit stress level - the best stress level could very likely be beyond the design limit. The real answers will require an assignment of relative importance to Type I and Type II errors. The use of stresses beyond design limits - overstress testing - was begun in the early 1980's, notably by the US Armed Forces, in an attempt to improve system reliability [5].
COSTS AND BENEFITS
The following cost-benefit analysis was developed in [4] as a method of 'netting out' all the positives and negatives relating to Environmental Stress Screening. The model allows for variables with unknown values to be estimated in terms of probability distributions, and the outcome calculated by Monte Carlo techniques. The output is a probability distribution of Net Present Savings per board tested. The software used was ‘Analytica”, published by Lumina Decision systems [6].
Figure 4 shows the relationships between the variables in the model. The costs of Type I errors are calculated in the node labeled ‘Cost of Test Failures’. The costs of Type II errors are calculated in the node labeled ‘total field Failure cost’. Since field failures occur, on average, at the MTTF, these must be discounted by the Cost of Capital to yield ‘Present Value of FF’, which can then be compared directly to ‘Cost of Test Failures’. The ‘NPS Importance’ node gives the relative importance of the variables in calculating Net Present Value. This will be discussed in a following section.
Figure 4Cost Model Variables and Relationships
It should be clear that cost considerations are not included in the definitions of Type I and Type II errors. The addition of cost in the model above allows us to evaluate the Net Present Savings per board generated by Final Test. The details of this model and the definitions of the mathematical relationships are given in [4]. Here we want to apply the model to 3 very different product scenarios in order to evaluate proposals to strengthen final Test and to reduce Type II errors.Table 4 shows the parameters for 3 products. Case 1 is for a fault-tolerant high-end Server, Case 2 is a Controller with a small imbedded processor, and case 3 is a telecommunications Router. The question in each case is should the Final Test be strengthened to Overstress status.
Variable Name
Units
Comments
Case 1: Server
Case 2: Controller
Case 3: Router
Cost of Inventory
%/week
Includes Depreciation and liquidity effects
Lognormal (0.5, 1.5)
Lognormal (0.5, 1.5)
Lognormal (0.5,1.5)
Test Failure Repair Cost
NP$
Material and Labor costs for debug and repair
Lognormal (1500, 1.5)
Lognormal (8,2)
Lognormal(1000,2)
Time to Repair Test Failure
Weeks
WIP time
Lognormal (6, 1.5)
Lognormal (.5,2)
Lognormal (1, .5)
Replacement Cost of Field Failure
Future$
Material and Labor (warranty costs)
Lognormal (2500, 1.25)
Linear (5,10)
Lognormal(190+0.52H, 1.5)
MTTF of Unscreened Unit
Years
Mean Time To Failure
Lognormal(5, 1.5)
8
Normal(20,2)
Impact of ESS on MTTF
%
Factor by which ESS improves unit MTTF
Normal (25%, 15%)
Normal (20%,15%)
Normal(20%, 15%)
Operational Costs
NP$
Variable cost only (no fixed costs)
Lognormal (50, 1.5)
5
Lognormal(20,2)
Whole Product Cost
NP$
Used to calculate inventory, depreciation, and replacement costs
5000
100
8000
ESS Yield
-
Probability of passing ESS screen
90%
90%
90%
IBP for Field Failure
Future$
A measure of the intangible costs
2500
Linear (20,40)
H/2
Cost of Capital
%/year
Time vs. money discount rate
15%
15%
15%
Table 4Input Variables for 3 Products
Once these values are input into the model, it calculates the probability of achieving Net Present Savings. For the Server, the results are shown in figure 5. Figure 5NPS for Server
From Figure 5, the cumulative probability of breaking even ($0 NPS) occurs at 0.3, meaning that there is a 30% probability of a negative NPS (costs exceed benefits, and the final Test looses money) and 70% probability of a positive NPS. The Expected Value of NPS, which is defined as 50% cumulative probability, is about $180. We expect this version of Final Test to save us $180 per board tested. Therefore, this program should be implemented.
Typically, a few uncertain inputs are responsible for most of the uncertainty in the final result. I have had opponents of overstress testing argue, for example, that the cost of repairing Type I failures would make the entire test worthless. This type of question is best answered by using Importance analysis – which, in statistical terms, is the absolute rank-order correlation between the sample of output values and the sample for each uncertain input. (See [6]).
Figure 6 shows the Importance analysis for the Server. Here we see that ‘Impact of ESS on MTTF’ is an order of magnitude more important than ‘Test Failure Repair Cost’ – and thus, if the model is to be challenged or improved, one should focus on Impact of ESS.
Figure 6Variable Importance for Server
Looking at Figure 7, NPS for an Embedded controller, the cumulative probability of breaking even ($0 NPS) occurs at 0.9, meaning that there is a 90% probability of a negative NPS (costs exceed benefits, and the final Test looses money) and 10% probability of a positive NPS. The Expected Value of NPS, which is defined as 50% cumulative probability, is about -$3.00. We expect this version of Final Test to loose $3 per board tested. Therefore, this program should not be implemented. Looking at the input values, we suspect that this conclusion is dominated by the high reliability of the unscreened board, and the low cost of a field failure.
Figure 7NPS for Controller
Variable importance for the controller is shown in Figure 8. Note that once again the impact of ESS on MTTF is the leading contributor to uncertainty in the final result of NPS. Also, importance is only calculable for variables, not input constants. Therefore, for example, operational costs which were variable for the server and show up on the ‘importance’ chart, are input as constant for the controller, and do not appear on the importance plot.
Figure 8Variable Importance for Controller
Turning to the case of the Router in figure 9, the probability of breaking even ($0 NPS) occurs at 0.4, meaning that there is a 40% probability of a negative NPS (costs exceed benefits, and the final Test looses money) and 60% probability of a positive NPS. The Expected Value of NPS, which is defined as 50% cumulative probability, is $52. We expect this version of Final Test to save us $52 per board tested. Here the risks are high, and the outcome is uncertain. A good policy would be to go back and re-evaluate the input parameters, or to run a preliminary test in an effort to reduce uncertainty.
Figure 9NPS for Router
Router Variable Importance in Figure 10 shows Impact of ESS again the leading cause of uncertainty, but now Test Failure Repair costs are significant.
Figure 10Variable Importance for Router
Finally, we can extract from the preceding analyses the costs of Type I and Type II errors for each of the 3 cases being examined. These results are shown in Table 5. Note particularly how expensive a Type II error is compared to Type I, and the importance of including the cost of money in discounting Type II errors to current dollars for MTTF years. I believe that information like that given in Table 5 can serve well to overcome the reluctance to consider overstress testing. The bias against overstress is often based on fear of creating additional Type I errors.
Server
Controller
Router
Type I error (cost of test fail)
$201.00
$1.13
$146.00
Type II error (field failure)
$5,063.00
$37.50
$8,566.00
MTTF (years)
5
8
20
Type II error in current $
$2,486.00
$14.62
$501.00
Table 5Cost of Type I and Type II errors
Conclusions
Optimizing the final Test can be done in a systematic manner, using statistically represented variables where the true values are unknown at the time of the analysis. The decision of which 'Final Test’ to employ can be analyzed in terms of Type I and Type II errors (false failures and false passes), and calculation of Net Present Savings per board to be realized by the test.Overstress tests can be more effective than either burn-in or conformance, depending on product parameters such as MTTF and cost of repair. The analysis shows that improving the MTTF of the product is the predominately important variable.Each product must be analyzed. Variations from product to product are key, with variables assuming vastly different importance for different products.Type II failures (field failures) are often an order of magnitude more costly than Type I failures (test failures in-house).
References
- Statistical Analysis for Engineers and Scientists, J. Wesley Barnes, McGraw-Hill, 19942. Burn-In Testing, Dmitri Kececioglu and Feng-Bin Sun, Prentice Hall, 19973. Burn-In, Finn Jensen and Neils Eric Petersen, Wiley, 19824. “The Politics of Accelerated Stress Testing”, Edmond L. Kyser, Eugene Hnatek and Mark Roettgering, Proc. IEST, March 20005. Environmental Stress Screening, Dmitri Kececioglu and Feng-Bin Sun, Prentice Hall, 19956. Analytica Users Guide, Lumina Decision Systems, 1999
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